1. Field of the Invention
The present invention relates to lithography techniques and in particular to a polarization analyzing system, an exposure method, and a method for manufacturing a semiconductor device
2. Description of the Related Art
To maximize integration of device components in an available semiconductor wafer area to fit more components in the same area, increased IC miniaturization is utilized. Reduced dimension of features formed on the semiconductor wafer are needed for increased integration density to meet the requirement of very large scale integration (VLSI). As the dimensions of the features are reduced, the features must be aligned with a greater and greater degree of precision. In a manufacturing process for the MOS transistor, a gate electrode also continues to shrink in size over time. Therefore, increased preciseness in an ion implantation process is required. Such gate electrode of the MOS transistor is disposed on the wafer like a step pattern extended in a predetermined direction. When a resist pattern, perpendicular to the step pattern is formed over the step pattern on the wafer by lithography process, residual resists may remain at an orthogonal point of the step pattern and the resist pattern, or a line width of the resist, pattern may be decreased at the orthogonal point. In Japanese Patent Laid-Open Publication No. Hei5-226226, a method for preventing the decrease of the line width is described. In the method, an illumination light is polarized such that the electric field of the illumination light is only perpendicular to the step pattern. However, a method for reducing the residual resist has not been proposed. Although the optical proximity effect correction (OPC) method is widely spread to reproduce a designed circuit pattern on the wafer, such OPC method has not been effective in reducing the residual resist remaining at the orthogonal point of the step pattern and the resist pattern.